1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistor structures, requiring highly doped shallow junctions in combination with a low series resistance.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently, and in the foreseeable future, the majority of integrated circuits are, and will be, based on silicon devices, due to the high availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern CPUs and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions, i.e., source and drain regions, which nevertheless exhibit a high conductivity so as to minimize the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions. The requirement for shallow junctions having a high conductivity is commonly met by perform-ing an ion implantation sequence to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure and, therefore, one or more anneal cycles are typically required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage. However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability in turn is limited by the solid solubility of the dopants in the silicon crystal and the temperature and duration of the anneal process that are compatible with the process requirements. Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a loss of dopant atoms in the extension regions, thereby “blurring” the dopant profile.
Thus, on the one hand, a high anneal temperature may be desirable in view of a high degree of dopant activation and re-crystallization of implantation-induced lattice damage, while, on the other hand, the duration of the anneal process should be short in order to restrict the degree of dopant diffusion, which may reduce the dopant gradient at the respective PN junctions and also reduce the overall conductivity due to reducing the averaged dopant concentration. Furthermore, very high temperatures during the anneal process may negatively affect the gate insulation layer, thereby reducing the reliability thereof. That is, high anneal temperatures may degrade the gate insulation layer and thus may influence the dielectric characteristics thereof, which may result in increased leakage currents, reduced breakdown voltage and the like. Therefore, for highly advanced transistors, the positioning, shaping and maintaining of a desired dopant profile are important properties for defining the final performance of the device.
In an attempt to reduce the overall series resistance of the current path in the transistor devices, not only the channel length is reduced but also the resistance of portions of the drain and source regions is lowered by the incorporation of metal silicide, which typically exhibits a lower sheet resistance compared to silicon, even if highly doped. For example, nickel is a refractory metal that is frequently used in advanced transistors for locally increasing the conductivity of doped silicon areas due to the moderately low resistance of nickel silicide compared to other metal silicides. For example, nickel silicide regions may be formed in restricted surface areas of the drain and source regions and in the gate electrode to provide increased conductivity in these areas. Unfortunately, the desired high conductivity of nickel silicide is typically accompanied with severe process non-uniformities occurring during the formation of respective nickel silicide regions, wherein a highly non-uniform interface is created between the doped semiconductor regions and the nickel silicide. Even so-called nickel pipes, i.e., silicide protrusions of significant length, may be created during the silicidation process. These silicide protrusions may extend into the channel region of the transistor and may therefore significantly affect the overall behavior of the transistor, which may even include a short of the PN junction, thereby causing a transistor failure. The non-uniformity of the nickel silicide process may, among others, depend on the diffusion conditions in the respective doped silicon areas, and, thus, the doped concentration, the crystallinity of silicon and the temperature may represent important factors for the result of the silicidation process. Thus, the degree of silicide failures due to nickel silicide tunnels in respective channel regions may depend on the complex history of the device and the respective silicidation parameters, wherein the silicidation defects may affect certain device areas more strongly compared to other device areas.
As is evident from the above-described situation during manufacturing sophisticated transistor devices, a plurality of complex interdependencies exist between many mechanisms for increasing the overall drive current capability of transistors, wherein the situation may even further increase in complexity when additional strategies for enhancing transistor performance are incorporated into the manufacturing sequence. For example, a certain type of strain may be intentionally created in the respective channel regions in order to increase the respective charge carrier mobility, which directly translates into a reduction of the channel resistance. In some approaches, stressed layers are provided in the vicinity of the channel regions to transfer stress forces into the channel region. In other strategies, strained semiconductor material may be used as strain-inducing sources. Also, in these cases, the provision of strained semiconductor materials, stressed overlayers and the like may have a significant influence on the previously described processes with respect to increasing the drive current capability by providing well-defined dopant profiles and highly conductive metal silicide regions, since, for instance, the diffusion behavior of a refractory metal may depend on the presence of non-silicon species, such as germanium, carbon and the like.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.